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19.3.2.4.1 Frequency Generation (FRG)
Frequency generation (see Figure 19.17 (p. 254) ) can be achieved in compare mode by:
? Setting the counter in up-count mode
? Enabling buffering of the TOP value.
? Setting the CC channels overflow action to toggle
Figure 19.17. TIMER Up-count Frequency Generation
TIMERn_TOP
0
TIMERn_CCx_CCV
The output frequency is given by Equation 19.2 (p. 254)
TIMER Up-count Frequency Generation Equation
f FRG = f HFPERCLK / ( 2^(PRESC + 1) x (TOP + 1) )
(19.2)
19.3.2.5 Pulse-Width Modulation (PWM)
In PWM mode, TIMERn_CCx_CCV is buffered to avoid glitches in the output. The settings in the
Compare Output Action configuration bits are ignored in PWM mode and PWM generation is only
supported for up-count and up/down-count mode.
19.3.2.6 Up-count (Single-slope) PWM
If the counter is set to up-count and the Compare/Capture channel is put in PWM mode, single slope
PWM output will be generated (see Figure 19.18 (p. 254) ). In up-count mode the PWM period is TOP
+1 cycles and the PWM output will be high for a number of cycles equal to TIMERn_CCx_CCV. This
means that a constant high output is achieved by setting TIMER_CCx to TOP+1 or higher. The PWM
resolution (in bits) is then given by Equation 19.3 (p. 254) .
Figure 19.18. TIMER Up-count PWM Generation
TIMERn_TOP
TIMERn_CCx_CCV
0
TIMn_CCx
Overflow
Com pare m atch
Buffer update
TIMER Up-count PWM Resolution Equation
R PWM up = log(TOP+1)/log(2)
The PWM frequency is given by Equation 19.4 (p. 254) :
TIMER Up-count PWM Frequency Equation
f PWM up/down = f HFPERCLK / ( 2^PRESC x (TOP + 1)
(19.3)
(19.4)
2011-04-12 - d0001_Rev1.10
254
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